This invention relates to integrated circuits. More particularly, this invention relates to a circuit configuration for reducing the impact of total ionizing radiation effects which lead to degradation in performance and overall functionality of CMOS integrated circuits.
FIG. 1 shows a cross section of a typical CMOS integrated circuit. The circuit shown and described is a p-well circuit. However, it will be apparent to those of ordinary skill in the art that this discussion also applies to n-well circuits by simply interchanging n-type and p-type structures or twin well circuits.
In FIG. 1, an n-type semi-conductor substrate 10, including an n-channel region 34 and a p-channel region 36, is provided for forming the integrated circuit thereon. P-channel devices, such as a p-channel transistor M2, are formed in the n-type substrate 10 by diffusing or implanting a source 12 and a drain 14. In the circuit of FIG. 1, the source 12 of the transistor M2 is coupled to a positive voltage supply Vdd. In typical CMOS circuits, a Vdd to substrate contact is formed of an n+ diffusion 16.
Further, a p-well 18 is formed in the n-type substrate 10. The exemplary integrated circuit illustrated in FIG. 1 also includes an n-channel transistor M1 with a drain 20 and a source 22 formed within the p-well 18 by diffusion or implantation. The source 22 is coupled to ground. A Vss to p-well contact is formed of a p+ diffusion 24 which is also coupled to ground. A p-channel gate 26 of the transistor M2 is formed over a layer of gate insulating oxide 28 in the p-channel region 36 between the source 12 and the drain 14. Similarly, a gate 30 is formed on a layer of gate insulating oxide 32 between the drain 20 and the source 22 of the n-channel transistor M1 in the p-well 18. This circuit is controlled by a voltage Vin applied to the two gates 26 and 30. The p-channel drain 14 is electrically coupled to the n-channel drain 20. The output of this circuit is a signal Vo formed on the two drains 14 and 20.
FIG. 2 illustrates a more detailed cross section of a typical CMOS integrated circuit. The integrated circuit of FIG. 2 includes a parasitic field transistor M3 in addition to the transistors M1 and M2 shown in FIG. 1. The parasitic field transistor M3 shown in FIG. 2 is an n-channel transistor and includes a gate 40 formed on a layer of field insulating oxide 38 between the drain 20 and the n+ diffusion 16.
Ionizing radiation occurs naturally in the form of charged particles that possess enough energy to break atomic bonds and create electron and hole pairs in an absorbing material. These charged particles may include protons, electrons, atomic ions, and photons with energies greater than a bandgap of the absorbing material. When typical integrated circuits, such as the CMOS integrated circuits described above and shown in FIGS. 1 and 2, are exposed to the charged particles over a period of months or even years, the ionizing radiation can contribute to a total ionizing dose. The total ionizing dose can have detrimental long term effects on the typical integrated circuit including circuit performance degradation and functional failure.
For example, as the charged particles pass through MOS devices, such as those shown in FIGS. 1 and 2, they generate electron and hole pairs which can be trapped in the gate oxides 28 and 32 (FIGS. 1 and 2) and the field oxide 38 (FIG. 2). Mobile electrons quickly transport through the field oxide 38 through the gate oxides 28 and 32, however, the holes have a low effective mobility and are easily trapped in the gate oxides 28 and 32 and the field oxide 38. The trapped holes, creating a positive oxide charge, shift threshold voltages of the transistors M1, M2 and M3 in a negative direction. Further, as the charged particles pass through MOS devices, interface states also increase. This increase in the interface states shifts the threshold voltages in the positive direction for n-channel devices, such as the transistor M1 and M3, and in the negative direction for p-channel devices, such as the transistor M2. Generally, the positive oxide charge shift is greater than the interface states shift. As a result, the magnitudes of the threshold voltage of the n-channel transistors M1 and M3 decrease while the magnitude of the threshold voltage of the p-channel transistor M2 increases.
In addition to the positive oxide shift and the interface states shift described above with respect to n-channel and p-channel devices, threshold voltage shifts caused by charged particles further affect parasitic MOS elements, such as the parasitic transistor M3 of FIG. 2. For example, as the threshold voltage of parasitic n-channel transistor M3 decreases, channels begin to form around the drawn n-channel transistor M1 and leakage currents flow around the edges of the n-channel gate region 30. Leakage currents begin to flow from the drain 20 to the source 22. Further, leakage currents also begin to flow from the drain 20 and source regions 22 of the drawn n-channel transistor M1 to the n-type substrate 10 or the n-well through the parasitic field transistor M3. These leakage currents may cause parametric failure to occur before functional failures.
The effects of these charged particles lead to the degradation of performance and ultimate failure of the CMOS devices. The additional radiation-induced interface states degrade the circuit performance by reducing the channel mobility, which as a result decreases channel conductance and transistor gain. Over time, the threshold voltages of the n-channel and p-channel devices may shift to a degree where the n-channel transistors cannot be turned off and the drive capability of the p-channel transistors is not sufficient for the circuit to continue operating at the system clock rate. Such a shift in threshold voltages of either the n-channel or p-channel transistors will cause the circuit to fail.
In addition to the concerns of long term total ionizing dose effects from radiation, there are also concerns of single event effects. Like total ionizing dose effects, single event effects occur because of galactic cosmic rays, solar enhanced particles, and energetic protons and neutrons. However, unlike the total ionizing dose effects, the failure of the circuit due to these single event effects are immediate and do not rely on a cumulative bombardment of charges and the like. Within the scope of single event effects, there are two common categories of single event failures which comprise the following: single event latch up and single event upset.
A first common type of failure is the single event latch up. In CMOS devices containing both n-channel and p-channel devices on a silicon substrate, parasitic bi-polar transistors exist. Latch-up is a well understood and documented phenomenon resulting from parasitic bipolar transistors. FIG. 3 shows the cross section of the integrated circuit of FIG. 1 with a pair of parasitic bipolar transistors T1 and T2 coupled as a Semiconductor Controlled Rectifier (SCR). The transistor T1 is a parasitic pnp transistor. The transistor T2 is a parasitic npn transistor. The emitter of the transistor T1 is formed of the p+ source diffusion 12 of the p-channel transistor. The base of the transistor T1 and the collector of the transistor T2 are formed of the n-type substrate 10. The collector of the transistor T1 and the base of the transistor T2 are formed of the p-well diffusion 18. The emitter of the transistor T2 is formed of the n+ source diffusion 22 of the n-channel transistor. A parasitic impedance Rs is formed in the substrate 10 between the base and the emitter of the parasitic pnp transistor T1. A parasitic impedance Rw is formed in the p-well 18 between the base and emitter of the parasitic npn transistor T2. FIG. 4 shows an equivalent circuit for the parasitic bipolar transistors of FIG. 3.
In the event of a radiation strike into the substrate 10, the radiation induced electron/hole pairs inject current into the base of the pnp transistor T1 causing the transistor to conduct unwanted current and enter the saturation phase of operation. The unwanted current passing through the saturated transistor T1 is driven through the parasitic impedance Rw.
The impedance Rw is coupled across the base-emitter junction of the transistor T2. If the value of the impedance Rw times the unwanted current is sufficiently high, the voltage across the impedance Rw can exceed the turn on potential for the transistor T2 causing it to conduct current. If the value of the impedance Rs times the current through the transistor T2 is sufficient to form a voltage large enough to hold the transistor T1 on, then latch-up has occurred. Thus, the transistors T1 and T2 now hold each other in an active and latched condition. This latch-up condition is a self sustaining high current condition which typically causes thermal runaway, which if let unchecked may permanently damage the circuit. Typically, normal operation of the circuit can only be recovered by removing the positive voltage supply Vdd.
The layout for a CMOS circuit which has improved immunity to radiation induced latch up is clearly described in U.S. Pat. No. 5,406,513, issued Apr. 11, 1995, Canaris et al. This referenced patent entitled MECHANISM FOR PREVENTING RADIATION INDUCED LATCH-UP IN CMOS INTEGRATED CIRCUITS is incorporated in its entirety herein by reference.
A second common type of failure in CMOS integrated circuits, the single event upset (SEU) occurs when a data bit or logic state in such a device can be corrupted if exposed to an ionized particle, such as an xcex1 particle or heavy ion, and current induced by a particle hit flows from n-type diffusion to a p-type diffusion. Thus, for example, a xe2x80x9c1xe2x80x9d can be upset in an NMOS static RAM and a xe2x80x9c0xe2x80x9d can be upset in an PMOS static RAM cell. The improved design of static RAM cells, latch memories, and flip/flop type memories are clearly described in U.S. Pat. No. 5,111,429 issued May 5, 1992, Sterling R. Whitaker. This referenced patent entitled SINGLE EVENT UPSET HARDENING CMOS MEMORY CIRCUIT is incorporated in its entirety herein by reference.
The present invention is a CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors can be formed in the p-well, and a network of PMOS transistors can be formed in the n-type substrate. Preferably, a contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Preferably, another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic are preferably dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.
Immunity to radiation induced latch up is improved by preferably utilizing a p+ guard ring electrically coupled to a first back bias voltage and formed inside the p-well between the n-channel transistors and the edge of the p-well. Preferably, the p+ guard is continuous and surrounds the n-channel transistors completely. Similarly, an n+ guard ring electrically coupled to a second back bias voltage is formed outside the p-well between the p-channel transistors and the edge of the p-well. Preferably, the n+ guard is also continuous and completely surrounds the p-channel transistors. With the p+ guard and n+ guard configured as described, in the event of a radiation hit, the guard rings operate to preferably reduce the parasitic impedance in the collector circuits of the parasitic bipolars forming a silicon controlled rectifier. Further, the guard rings also preferably act as additional collectors of radiation induced current.
Immunity to radiation induced single event upset is preferably improved by forming duplicate functions in an n-channel network and a p-channel network. The networks are configured such that n-channel control transistors are coupled to control p-channel load transistors and p-channel control transistors are coupled to control n-channel load transistors. This configuration of the transistor networks helps prevent single event upsets from affecting the circuit.